Automatic tool for test set generation and DfT assessment in analog circuits

This work presents a low cost automatic test generation tool for structural analog testing. With the spice netlist and technology models of the circuit to be tested, a fault list is generated, considering a defect modeling provided by the user. The tool interacts with a spice simulator, simulating the fault-free and faulty circuits. The test development considers DC, AC (single tone) and transient (step) stimuli applied at the primary circuit inputs, computing the obtained fault coverage when taking different circuit nodes as observation points. The final test set determination relies on a fault dictionary that helps maximizing the fault coverage, at the same time as minimizing the test application. Since different circuit nodes are observed during the fault simulation campaign, this tool also helps the test developers and designers on defining Design-for-Testability strategies to increase fault detection by covering the undetected faults identified. The feasibility of the proposed method and the applicability of the tool are demonstrated with two case-studies, consisting in fully-differential integrated filters designed on a commercial 180 nm process. Results show that fault coverages near to 95% are obtained in both case-studies while requiring small test sequences with simple parametric measurements.