共 50 条
- [41] Design of Parallel BCH Decoder for MLC Memory ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3, 2008, : 687 - 688
- [42] A memory efficient serial LDPC decoder architecture 2005 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS 1-5: SPEECH PROCESSING, 2005, : 41 - 44
- [43] Fault secure encoder and decoder for memory applications DFT 2007: 22ND IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2007, : 409 - 417
- [44] HIERARCHICAL MODEL OF MEMORY AND MEMORY LOSS JOURNAL OF PHYSICS A-MATHEMATICAL AND GENERAL, 1988, 21 (23): : 4443 - 4454
- [45] The Palestine Nakba: Decolonizing History, Narrating the Subaltern, Reclaiming Memory MIDDLE EAST JOURNAL, 2012, 66 (04): : 747 - 749
- [47] Parallel low memory size turbo decoder 2003 INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY, VOL 1 AND 2, PROCEEDINGS, 2003, : 874 - 877
- [48] "Mixing memory": discovering and narrating the other selves of Alzheimer's PROSE STUDIES-HISTORY THEORY CRITICISM, 2021, 42 (01): : 53 - 67
- [49] FPGA Implementation of BCH Decoder for Memory Systems PROCEEDINGS OF THE 2015 INTERNATIONAL CONFERENCE ON APPLIED AND THEORETICAL COMPUTING AND COMMUNICATION TECHNOLOGY (ICATCCT), 2015, : 542 - 547
- [50] A memory-efficient progressive JPEG decoder 2007 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERS, 2007, : 8 - +