共 10 条
- [1] Mechanical effects of copper through-vias in a 3D die-stacked module 52ND ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2002 PROCEEDINGS, 2002, : 473 - +
- [2] Functional Testing of AI Cores through Thinned 3D I/O Buffer Dies in 3D Die-Stacked Modules IEEE 72ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2022), 2022, : 977 - 980
- [3] Smart refresh: An enhanced memory controller design for reducing energy in conventional and 3D die-stacked DRAMs MICRO-40: PROCEEDINGS OF THE 40TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, 2007, : 134 - +
- [5] 3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer Bonding with copper Through Silicon Vias (TSV)ac 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, 2009, : 12 - +
- [6] Token3D: Reducing Temperature in 3D Die-Stacked CMPs through Cycle-Level Power Control Mechanisms EURO-PAR 2011 PARALLEL PROCESSING, PT 1, 2011, 6852 : 295 - 309
- [7] 3D stacked flip chip packaging with through silicon vias and copper plating or conductive adhesive filling 55TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2005 PROCEEDINGS, 2005, : 795 - 801
- [8] Multi-stacked flip chips with copper plated through silicon vias and re-distribution for 3D system-in-package integration ENABLING TECHNOLOGIES FOR 3-D INTEGRATION, 2007, 970 : 179 - +