3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer Bonding with copper Through Silicon Vias (TSV)ac

被引：0

作者：

Van Olmen, J. ^{[1
]}

Coenen, J. ^{[1
]}

Dehaene, W. ^{[2
]}

De Meyer, K. ^{[2
]}

Huyghebaert, C. ^{[1
]}

Jourdain, A. ^{[1
]}

Katti, Guruprasad ^{[2
]}

Mercha, A. ^{[1
]}

Rakowski, M. ^{[1
]}

Stucchi, M. ^{[1
]}

Travaly, Y. ^{[1
]}

Beyne, E. ^{[1
]}

Swinnen, B. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Louvain, Belgium

[2] K U Louvain, EE Dept, Louvain, Belgium

来源：

2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION | 2009年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we demonstrate functional 3D circuits obtained by a 3D Stacked IC approach using Die-to-Wafer Hybrid Collective bonding with Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 130nm CMOS process on 200mm wafers. The top die Is thinned down to 25 mu m and bonded to the landing wafer by a combination of polymer bonding and copper to copper thermocompression bonding. Top and landing wafers contain CMOS finished with 2 levels of metal in Copper/Oxide. Ring oscillators consisting of inverters distributed over both top and bottom dies Interconnected through up to 40 TSVs are used to demonstrate the process. This paper focuses on integration Issues solved during process development and electrical characterization of the obtained TSVs.

引用

页码：12 / +

页数：2

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