New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies

This paper describes new sleep-based positive feedback source-coupled logic (PFSCL) tri-state inverter/buffer topologies. The tri-state behavior is obtained by disconnecting the circuit from both power supply and ground. This is achieved by placing additional transistors, driving the load transistor to cut off or disabling the current source. The combination of the three methods results in six new topologies. The functionality and performance of the proposed topologies is studied through SPICE simulations. A comparison with available sleep-based PFSCL tri-state buffer circuit shows a maximum reduction of 11% and 60% in the propagation delay and output enable time, respectively. The usefulness of the proposed topologies is illustrated through bus and D latch implementation.