Contact Resistance of Solder Bump with Low Cost Photosensitive Polyimide for High Performance SoC

被引：0

作者：

Park, Jongwoo ^{[1
]}

Hong, Jungpyo ^{[1
]}

Lee, Miji ^{[1
]}

Sun, Dongyoon ^{[1
]}

Kang, Kyung ^{[2
]}

Kim, Taesung ^{[3
]}

Kim, Seungwon ^{[3
]}

Kwon, Sujin ^{[3
]}

Joo, Changkyu ^{[1
]}

Ha, Sangsu ^{[1
]}

Kim, Wooyeon ^{[1
]}

Ryu, Jongsu ^{[1
]}

Pae, Sangwoo ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, Syst LSI Business, Qual & Reliabil, San 24, Yongin 446711, Gyeonggi Do, South Korea

[2] Samsung Elect Co Ltd, Syst LSI Business, Photo Bump Proc, Yongin 446711, Gyeonggi Do, South Korea

[3] Samsung Elect Co Ltd, Syst LSI Business, R&D Ctr, Yongin 446711, Gyeonggi Do, South Korea

来源：

2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2015年

关键词：

Bump resistance; far back-end-of line process; photosenstive polyimide; outgassing; physical vapor desposition; residual gas analysis; reliability qualification;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

One of technical hurdles in far back-end of line (FBEOL) process is to assure lower solder bump contact resistance (Rc) associated with photosensitive polyimide (PSPI) and under bump metal (UBM) process. Often, higher bump Rc results in low Vcc shift fails in high performance SoC product. With palpable understanding of outgassing behaviors of PSPI and meticulous characterization of degassing phenomena linked to plasma etch with physical vapor deposition (PVD), we successfully achieved < 10m Omega bump Rc even with a low cost PSPI without an existing PVD refurbishment. From photo process to package reliability, a far back-end process optimization for cost effective bump production will be presented.

引用

页数：2

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