An on-line correction technique of random loading with a real-time signal processor for a laboratory fatigue test

被引:0
|
作者
Li, M [1 ]
Wu, YS
Xu, BH
Jia, WJ
Zhao, W
机构
[1] City Univ Hong Kong, Dept Comp Sci, Kowloon, Hong Kong, Peoples R China
[2] Chinese Acad Engn, China Ship Sci Res Ctr, Wuxi 214082, Peoples R China
[3] Texas A&M Univ, Dept Comp Sci, College Stn, TX 77843 USA
关键词
fatigue test; on-line correction of random loading; optimal control;
D O I
暂无
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
The authors present an application of the Solartron 1200 Real Time Signal Processor to correcting the on-line random loading in a fatigue test system. By inputting a power spectrum described by a data die to a computer, its corresponding random process may be simulated. Since the processor is connected with a computer, results of signal processing done by the processor are sent to the computer periodically during the test. The computer performs pattern matching using the correlation coefficient value (CCV) between a loading spectrum and its predetermined target. If a CCV exceeds its threshold, the old data file will be replaced with a new one and the random loading exerted on a specimen will be updated. When the new data file is obtained based on optimal control strategy, the updated loading spectrum will approach its target. Therefore, an electrohydraulic fatigue test system equipped with a real-time signal processor can realize an on-line correction of a random loading based on the target spectrum desired. Since this updating does not change the original software package and hardware of the system, the performance of the system and testing quality are safely improved.
引用
收藏
页码:409 / 414
页数:6
相关论文
共 50 条
  • [41] SIGNAL PROCESSOR IMPLEMENTS ANALOG AND DIGITAL FUNCTIONS IN REAL-TIME
    SWAGER, AW
    EDN, 1991, 36 (22) : 95 - 96
  • [42] A Real-Time HDTV Signal Processor: HD-VSP
    Tamitani, Ichiro
    Harasaki, Hidenobu
    Nishitani, Takao
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 1991, 1 (01) : 35 - 41
  • [43] FFT-Processor for Real-Time Signal Processing.
    Kueng, R.
    Bulletin de l'Association suisse des electriciens, 1986, 7 (11): : 646 - 652
  • [44] A Low-Power Low-Latency Processor for Real-Time On-line Local Mean Decomposition
    Hsueh, Hsea-Ching
    Chien, Shao-Yi
    PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2015, : 205 - 208
  • [45] A2.79 competitive on-line algorithm for two processor real-time systems with uniform value density
    Qifan Y.
    Applied Mathematics-A Journal of Chinese Universities, 1997, 12 (3) : 333 - 342
  • [46] REAL-TIME PROGRAMMABLE PARALLEL DIGITAL SIGNAL PROCESSOR ARCHITECTURE
    BARR, PC
    BRESSEL, JG
    HARRIS, JD
    VALAS, CJ
    CA-DSP 89, VOLS 1 AND 2: 1989 INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING, 1989, : 558 - 562
  • [47] A MICROPROGRAMMABLE REAL-TIME VIDEO SIGNAL PROCESSOR (VSP) LSI
    YAMASHINA, M
    ENOMOTO, T
    KUNIO, T
    TAMITANI, I
    HARASAKI, H
    NISHITANI, T
    SATOH, M
    KIKUCHI, K
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (06) : 1117 - 1123
  • [48] IMPLEMENT COMPLEX ANALOG FILTERS WITH A REAL-TIME SIGNAL PROCESSOR
    HOLM, RE
    EDN MAGAZINE-ELECTRICAL DESIGN NEWS, 1979, 24 (21): : 171 - 180
  • [49] Efficient on-line processor scheduling for a class of IRIS (increasing reward with increasing service) real-time tasks
    Dey, Jayanta K.
    Kurose, James F.
    Towsley, Don
    Krishna, C.M.
    Girkar, Mahesh
    Performance Evaluation Review, 1993, 21 (01):
  • [50] A 2/5 competitive on-line algorithm for two processor real-time systems with uniform value density
    Yang, QF
    Shen, H
    6TH WORLD MULTICONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL V, PROCEEDINGS: COMPUTER SCI I, 2002, : 177 - 181