Circuit partitioning using graph-based alternative wiring technique

Circuit partitioning has always been one of the center tasks in VLSI physical design process. Recently, a so-called alternative wiring (rewiring) technique is proposed for perturbing the circuit logic while doing partitioning. This approach adds an additional room for partition improvement. However, the rewiring techniques used are all ATPG-based, which could be CPU intensive in larger circuits even with the recently developed speeding-up enhancements in locating alternative wires. In this paper, we propose using a newly developed graph-based circuit rewiring technique for doing circuit partitioning. The technique can perturb the circuit logic for partitioning improvements with a much faster speed: We applied this technique on MCNC benchmarks ranging from medium to large in size and obtained a reduction of 4.5% in cost on average. Experimental results show that this technique is very useful for large circuits.