Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits

被引：9

作者：

Ker, MD ^{[1
]}

Jiang, HC ^{[1
]}

Chang, CY ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Integrated Circuits & Syst Lab, Hsinchu, Taiwan

来源：

13TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/ASIC.2000.880752

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is greatly useful for high-frequency IC's, which need a very low input capacitance.

引用

页码：293 / 296

页数：4

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