A Triple-Mode LDPC Decoder Design for IEEE 802.11n System

被引：0
|
作者：
Chao, Min-An [1 ]
Wen, Jen-Yang [1 ]
Shih, Xin-Yu [1 ]
Wu, An-Yeu [1 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10764, Taiwan
来源：
ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 | 2009年
关键词：
ASSIGNMENT;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper shows a triple-mode LDPC decoder design with two design techniques, the matrix reordering algorithm for multi-mode reconfiguration and the Single-Entry-Multiple-Data (SEMD) scheme for throughput enhancement. The matrix reordering algorithm can reduce the computational complexity from O(n !) to O(n(3)). The SEMD can enhance the throughput by m times with small area overhead. With TSMC 0.13 mu m CMOS, the proposed design is synthesized in 1.99mm(2) area at 172.4MHz.
引用
收藏
页码：2445 / 2448
页数：4
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