POSTER: Reducing the Burden of Parallel Loop Schedulers for Many-Core Processors

被引：1

作者：

Arif, Mahwish ^{[1
]}

Vandierendonck, Hans ^{[1
]}

机构：

[1] Queens Univ Belfast, Belfast, Antrim, North Ireland

来源：

ACM SIGPLAN NOTICES | 2018年 / 53卷 / 01期

基金：

英国工程与自然科学研究理事会;

关键词：

D O I：

10.1145/3200691.3178517

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

This work proposes a low-overhead half-barrier pattern to schedule fine-grain parallel loops and considers its integration in the Intel OpenMP and Cilkplus schedulers. Experimental evaluation demonstrates that the scheduling overhead of our techniques is 43% lower than Intel OpenMP and 12.1 x lower than Cilk. We observe 22% speedup on 48 threads, with a peak of 2.8 x speedup.

引用

页码：383 / 384

页数：2

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