ATM switch architecture modelling under uniform and bursty traffic.

ATM switch architectures are investigated from a typology of traffic description. Classical results under uniform traffic are retrieved with the help of the VHDL simulator we developped. Then this modelization is extended to the case of bursty traffic in order to deduce new switch performance parameters. Since uniform traffic is analysed at the cell level whereas bursty traffic needs the ATM buffer or the burst lenght to exhibit indexes of performances, this temporal resolution is analysed through an extension of the classical parameters used for uniform traffic. The understanding of these new parameters allows for optimizing switch architecture when correlated cells in a larger scale than one burst (e.g. video source) are taken into account.