Efficient and high-performance pedestrian detection implementation for intelligent vehicles

被引:3
|
作者
Abid, Nesrine [1 ]
Ouni, Tarek [1 ,2 ]
Ammari, Ahmed C. [3 ]
Abid, Mohamed [1 ,2 ]
机构
[1] Sfax Univ, Natl Sch Engn Sfax, Lab Comp & Embedded Syst, Sfax, Tunisia
[2] Digital Res Ctr Sfax, Sfax, Tunisia
[3] Sultan Qaboos Univ, Coll Engn, Elect & Comp Engn Dept, Muscat 123, Oman
关键词
Multi-scale covariance descriptor; SVM classifier; Pedestrian detection; Multi-core architecture; Parallel implementation; Real-time embedded systems; REGION COVARIANCE; CLASSIFICATION; DESCRIPTOR; SCALE;
D O I
10.1007/s00530-021-00799-1
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Implementing pedestrian detection real-time embedded systems remains a major challenge. Detecting pedestrians in an advanced driver assistance system requires a lot of time and resources. The method based on Multi-Scale Region Covariance Descriptor (MSRCD) and Support Vector Machine (SVM) is one of the most effective approaches to perform pedestrian detection. However, such implementation is difficult to be executed in real time on embedded systems. This paper presents three improvements to adapt the solution based on the MSRCD descriptor and SVM classifier for embedded pedestrian detection. First, a new feature combination capable to provide the most accurate description at a minimum processing time for MSRCD is proposed. Second, to speed up the SVM classification, a new approach that adopts the mean SVM technique and Euclidian distance is proposed. Third, parallel implementation is exploited to accelerate processing time on multi-core architectures. The software implementation is performed using the INRIA data set. 18.94% processing time speed-up, 48.21% less memory usage, and 2.38% improved detection accuracy are achieved using the proposed descriptor. Moreover, 58.22% processing time speed-up is obtained for the proposed classifier while keeping the same testing accuracy. The parallel implementation is performed using dual ARM Cortex-A9 processors of a selected Xilinx zynq platform. The obtained results confirmed the effectiveness of the proposed parallelization at accelerating the computing time about 3 times the original sequential processing.
引用
收藏
页码:69 / 84
页数:16
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