On-line testing for VLSI

被引：2
|
作者：
Nicolaidis, M
机构：
来源：
ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY | 1997年
关键词：
D O I：
10.1109/TEST.1997.639731
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：1042 / 1042
页数：1
相关论文
共 50 条
  • [1] On-Line Testing for VLSI—A Compendium of Approaches
    M. Nicolaidis
    Y. Zorian
    [J]. Journal of Electronic Testing, 1998, 12 : 7 - 20
  • [2] On-line testing for VLSI - A compendium of approaches
    Nicolaidis, M
    Zorian, Y
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1998, 12 (1-2): : 7 - 20
  • [3] On-line testing for VLSI: state of the art and trends
    Nicolaidis, M
    [J]. INTEGRATION-THE VLSI JOURNAL, 1998, 26 (1-2) : 197 - 209
  • [4] ADOLT - An ADaptable On-Line Testing scheme for VLSI circuits
    Maamar, A
    Russell, G
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS, 1999, : 770 - 771
  • [5] A unified approach for off-line and on-line testing of VLSI systems
    Lala, PK
    Yang, S
    Busaba, F
    [J]. 1996 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 1996, : 195 - 203
  • [6] ON-LINE TESTING
    RUTLEDGE, WC
    [J]. TAPPI, 1973, 56 (02): : 4 - 5
  • [7] On-line planarity testing
    DiBattista, G
    Tamassia, R
    [J]. SIAM JOURNAL ON COMPUTING, 1996, 25 (05) : 956 - 997
  • [8] A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults
    Biswal, Pradeep Kumar
    Biswas, Santosh
    [J]. MICROELECTRONICS JOURNAL, 2015, 46 (07) : 598 - 616
  • [9] On-Line Testing of digital VLSI circuits at Register Transfer Level using High Level Decision Diagrams
    Biswal, Pradeep Kumar
    Biswas, Santosh
    [J]. MICROELECTRONICS JOURNAL, 2017, 67 : 88 - 100
  • [10] CMOS sensors for on-line thermal monitoring of VLSI circuits
    Szekely, V
    Marta, C
    Kohari, Z
    Rencz, M
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1997, 5 (03) : 270 - 276
12345