FPGA Based Low-Latency Market Data Feed Handler

被引：0
|
作者：
Zhou, Liyuan [1 ]
Jiang, Jiang [1 ]
Liao, Ruochen [1 ]
Yang, Tianyi [1 ]
Wang, Chang [1 ]
机构：
[1] Shanghai Jiao Tong Univ, Sch Microelect, 800 Dongchuan Rd, Shanghai 200240, Peoples R China
来源：
COMPUTER ENGINEERING AND TECHNOLOGY, NCCET 2014 | 2015年 / 491卷
关键词：
Market data handler; low latency; FAST; FPGA;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Financial market data refers to price and trading data transmitted between financial exchange instruments and traders. Delivery of financial market feeds requires massive data processing with ultra-low latency. FAST protocol is a financial technology standard for compressing data stream during network transmission. This paper presents the design and implementation of a hardware accelerator for financial market data in FAST protocol. We propose a parallel data decoding architecture for field analysis process, which is the key feature in our design. The decoder of this work is able to parse and filter FAST format messages, and with an additional parallel structure compared with typical handlers, achieving a 40% speedup on decoding time compared to previous attempts. The filter function is reconfigurable for various user preferences and further protocol updates. Test under massive source data indicated an average latency of 1.6 mu s per message.
引用
收藏
页码：69 / 77
页数：9
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