Influence of thermal annealing on the memory effect in MIS structures containing crystalline Si nanoparticles

Silicon nanocrystals embedded in a SiO2 matrix are fabricated by thermal annealing of Metal/SiO2/SiOx/c-Si structures (x=1.15) at 1000 degrees C in N-2 atmosphere for 30 or 60 min. High frequency C-V measurements demonstrate that both types of sample can be charged negatively or positively by applying a positive or negative bias voltage to the gate. The clockwise hysteresis windows of 30 and 60 min annealed samples are about 7 and 5.5 V for the +/- 12 V scanning range (E-ox = 2.4 MV/cm), respectively. Although the samples annealed for 60 min have a smaller hysteresis window, they have two important advantages compared to the 30 min annealed ones: a lower defect density at the c-Si wafer/SiO2 interface and a smaller value of the fixed oxide charge close to this interface.