NVM/DRAM Hybrid Memory Management with Language Runtime Support via MRW Queue

被引:0
|
作者
Nakagawa, Gaku [1 ]
Oikawa, Shuichi [2 ]
机构
[1] Univ Tsukuba, Dept Comp Sci, Tsukuba, Ibaraki 305, Japan
[2] Univ Tsukuba, Fac Engn Informat & Syst, Div Informat Engn, Tsukuba, Ibaraki 305, Japan
关键词
PHASE-CHANGE MEMORY;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Non-volatile memory (NVM), such as PCM, STT-MRAM, and ReRAM, makes it possible to integrate secondary storage into main memory. This integration reduces I/O access times to typically slow block devices; however, it is unrealistic to construct a large capacity main memory with a single NVM at this time, because NVM have disadvantages regarding write access. Combining NVM and other memory devices is necessary to hide such disadvantages. In particular, we should place writehot data on DRAM and write-cold data on NVM. For data placement, programming language runtime supports are useful, since they have more detailed information about write access than the operating system. A previous study proposed a method to manage NVM/DRAM hybrid memory with programming language runtime supports, determining data placement based on the number of write accesses to each object (i. e., the individual counting method); however, this approach has two problems, namely memory efficiency and determination of threshold values for data placements. The Most Recent Write (MRW) queue method is an alternative method to distinguish between write-hot data and write-cold data. MRW queue manages the frequency of write accesses to objects. In this study, we discuss the problems of the individual counting method and show solutions using the MRW queue approach. Results of our experimentation show that the MRW queue method improves memory efficiency and reduces overhead of the individual counting method.
引用
收藏
页码:357 / 362
页数:6
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