Compiler-Based Timing For Extremely Fine-Grain Preemptive Parallelism

被引:6
|
作者
Ghosh, Souradip [1 ]
Cuevas, Michael [1 ]
Campanoni, Simone [1 ]
Dinda, Peter [1 ]
机构
[1] Northwestern Univ, Dept Comp Sci, Evanston, IL 60208 USA
基金
美国国家科学基金会;
关键词
timing; preemptive scheduling; line-granularity parallelism; IMPLEMENTATION;
D O I
10.1109/SC41405.2020.00057
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In current operating system kernels and run-time systems, liming is based on hardware timer interrupts, introducing inherent overheads that limit granularity. For example, the scheduling quantum of preemptive threads is limited, resulting in this abstraction being restricted to coarse-grain parallelism. Compiler-based timing replaces interrupts from the hardware timer with callbacks from compiler-injected code. We describe a system that achieves low-overhead timing using whole-program compiler transformations and optimizations combined with kernel and run-time support. A key novelty is new static analyses that achieve predictable, periodic run-time behavior from the transformed code, regardless of control-flow path. We transform the code of a kernel and run-time system to use compiler-based timing and leverage the resulting fine-grain timing to extend an implementation of fibers (cooperatively scheduled threads), attaining what is effectively preemptive scheduling. The result combines the fine granularity of the cooperative fiber model with the ease of programming of the preemptive thread model.
引用
收藏
页数:15
相关论文
共 50 条
  • [41] OBTAINING A VERY FINE-GRAIN STRUCTURE IN A NICKEL-BASED ALLOY
    AUBERT, H
    SCRIPTA METALLURGICA, 1985, 19 (11): : 1335 - 1339
  • [42] A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating
    Ishihara, Shota
    Hariyama, Masanori
    Kameyama, Michitaka
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (08) : 1394 - 1406
  • [43] Fine-grain reconfigurable logic cells based on double-gate MOSFETs
    O'Connor I.
    Hassoune I.
    Navarro D.
    IFIP Advances in Information and Communication Technology, 2010, 313 : 97 - 113
  • [44] Efficient fine-grain computations based on remote DMA communication with rotating buffers
    Smyk, A
    Tudruj, M
    CONCURRENT INFORMATION PROCESSING AND COMPUTING, 2005, 195 : 243 - 252
  • [45] Design of a Fine-Grain Reconfigurable VLSI Based on Logic-In-Control Architecture
    Okada, Nobuaki
    Kameyama, Michitaka
    2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009), 2009, : 278 - 281
  • [46] Fine-grain layered multicast based on hierarchical bandwidth inference congestion control
    Lin, JL
    Pei, SC
    Hwang, JN
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 2667 - 2670
  • [47] RDMA communication based on rotating buffers for efficient parallel fine-grain computations
    Smyk, A
    Tudruj, M
    PARALLEL PROCESSING AND APPLIED MATHEMATICS, 2004, 3019 : 50 - 58
  • [48] FINE-GRAIN SCALABLE AUDIO CODING BASED ON ENVELOPE RESTORATION AND THE SPIHT ALGORITHM
    Hansen, Heiko
    Strahl, Stefan
    Mertins, Alfred
    2009 16TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING, VOLS 1 AND 2, 2009, : 539 - +
  • [49] Optional and responsive fine-grain locking in Internet-based collaborative systems
    Sun, CZ
    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2002, 13 (09) : 994 - 1008
  • [50] Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs
    O'Connor, Ian
    Hassoune, Ilham
    Navarro, David
    VLSI-SOC: DESIGN METHODOLOGIES FOR SOC AND SIP, 2010, 313 : 97 - 113