Design techniques for a CMOS low-power low-voltage fully differential flash analog-to-digital converter

被引：0

作者：

Lee, TS ^{[1
]}

Luo, LD ^{[1
]}

Lin, CS ^{[1
]}

机构：

[1] Natl Yunlin Univ Sci & Technol, Dept Elect Engn, Touliu 640, Yunlin, Taiwan

来源：

2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A CMOS 8-bit, 33.3MS/s flash ADC with +/-1.5V power supply is developed through the use of a CMOS low-power high-speed fully differential comparator. To achieve good signal-to-(noise and distortion) ratio in the presence of noisy digital circuitry, the architecture of the ADC is fully differential. The differential nonlinearity error in dynamical operation is less than +/-0.3LSB. Signal-to-(noise and distortion) ratio is 46.2dB at a sampling rate of 33.3MS/s and input frequency of 4MHz. The power dissipation is 10(6)mW at 33.3MS/s with +/-1.5V power supply.

引用

页码：357 / 360

页数：4

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