Piecewise-linear Modelling of CMOS Gates Propagation Delay as a Function of PVT Variations and Aging

Due to the aggressive scaling of transistor dimensions, which took place in the last decades, chip devices are exposed to high electric fields and current densities during normal operation. These working conditions trigger degradation phenomena that compromises the device functionality and rises questions regarding circuit reliability. In this paper we present a simulation based methodology that incorporates the aging phenomena, which might allow to address the reliability aspects during the design phase and pave the way for further life-time projections at the design stage. Piecewise-linear functions are used to model the propagation delays and estimate the correlation between the different degradation mechanisms and the PVT variations.