Optimal Designs of Reversible/Quantum Decoder Circuit Using New Quantum Gates

The need for a low energy dissipation circuit in place of irreversible circuits at a fast pace. Among the emerging technology is quantum computing technology has attracted many advanced features such as information lossless and low energy dissipation. The need for reduction of quantum cost, quantum delay in the fundamental circuit like decoder is of prominent importance. The low quantum cost and quantum delay means fast computation in the quantum logic circuits. In this article, we have synthesized 2 - to - 4 decoder on three approaches based on S(1)G, S(2)G and S(3)G gates. Then we propose on two approaches a new design of 3 - to - 8 decoder as well as n - to - 2(n) decoder by cascading the proposed 2 - to - 4 decoder with a new gate called S(4)G, The proposed design of a novel 2 - to - 4 decoder (approach 3) can obtain superiority in terms of the number of Quantum cost, Quantum delay and garbage outputs (7,5 and 1respectively) compared with the existed circuits. Also we have designed a novel 3 - to - 8 decoder based on two approaches. Which is obvious on the low quantum delay of 15, quantum cost 23 and garbage output 1. In addition, various lemmas have presented to fix the quantum cost, quantum delay and garbage output for the design of n - to - 2(n) decoder. In the proposed 3 - to - 8 decoder design the rate of quantum cost, quantum delay and garbage outputs is 28%, 53% and 33% respectively less than the existing designs.