A modeling platform for efficient characterization of phase-locked loop Δ-Σ frequency synthesizers

被引：0
|
作者：
Bourdi, Taoufik [1 ]
Borjak, Assaad [2 ]
Kale, Izzet [2 ,3 ]
机构：
[1] Beceem Commun Inc, Santa Clara, CA 95054 USA
[2] Univ Westminster, Dept Elect Syst, Appl DSP & VLSI Res Grp, London, England
[3] Eastern Mediterranean Univ, Appl DSP & VLSI Res Ctr, Famagusta, Turkey
来源：
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年
关键词：
fractional-N; Delta-Sigma; synthesizer; PLL; charge pump; PFD; VCO; divider; prescaler;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
To dramatically reduce the need for Silicon reproduction due to poor noise performance, a close-loop simulation platform that combines both measured and/or simulation results of open-loop PLL sub-blocks has been developed. The platform is suited for Delta-Sigma based fractional-N frequency synthesizers enabling integrated circuit designers to directly meet cost, performance and schedule milestones. Case studies employing the developed platform are provided for a fractional-N frequency synthesizer operating near 5 GHz. The effects of dead-zone, dithering, near-integer divisor operation, noise folding and prescaler usage on the overall phase noise performance of the entire frequency synthesizer are detailed.
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页码：3221 / +
页数：2
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