Bumpless flip chip packages

Current flip chip packaging activities are divided into two very different approaches. One is to further improve the bumped structure with particular focus on bump structure, lead-free, under-fill material and board level reliability issues. The other is to develop the ultimate structure without bumps to achieve even better electrical characteristics and meet more stringent environmental specifications. This paper presents a novel bumpless flip chip package for cost/performance driven devices. Using the electrochemical plating (ECP) method, a pattern of fine-line traces down to 25 mum line/space is fabricated and connected to the die pads directly without using wire-bonds or solder bumps or an interposer substrate or vacuum processes such as thin film sputtering. This method enables the production of area array packages up to 256 I/O using a single layer of metal. Package-to-board level connection is made through a series' of resin-filled terminals which provide excellent mechanical compliancy between the package and the assembled board. The electroplated fine-line traces which provide signal re-distribution in this package are similar to those in wafer level packages. More importantly, their "fanout" feature is the key to enabling high lead count devices to be accommodated in the area array formal with this package. Details of the design - concepts and processing technology associated with this package are discussed. Considerations for various cost/performance devices are discussed. Finally, the importance of design integration early in the technology development cycle with package-level and board-level reliability is highlighted as a critical path to an optimal design for cost-driven and/or performance-driven devices.