A 1.08-Gb/s Burst-Mode Clock and Data Recovery Circuit Using the Jitter Reduction Technique

A 1.08-Gb/s CMOS half-rate burst-mode clock and data recovery (BMCDR) circuit with a novel jitter reduction technique is presented. There are several discrete delay time values in the programmable delay circuit (PDC) of the edge detector can be selected by five addressing inputs to create a "dynamic average" delay time that equals to half-of-data period (T-bit/2) to ensure minimum jitter accumulation. A prototype chip was designed with TSMC 0.18-mu m CMOS 1P6M technology. The occupied die area of the CDR is 0.99 x 0.97 mm(2), and the power consumption is 36 mW under a 1.8-V supply voltage.