共 50 条
- [31] Seven-level inverter with reduced blocking voltage and self-balancing of capacitors [J]. Dianji yu Kongzhi Xuebao/Electric Machines and Control, 2020, 24 (03): : 97 - 105
- [33] Simple PWM technique of capacitor voltage balance for three-level inverter with DC-link voltage sensor only [J]. IECON 2007: 33RD ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, VOLS 1-3, CONFERENCE PROCEEDINGS, 2007, : 1749 - +
- [34] Novel SVPWM strategy considering DC-link balancing for a multi-level voltage source inverter [J]. Conf Proc IEEE Appl Power Electron Conf Expo APEC, (509-514):
- [35] A novel SVPWM strategy considering DC-link balancing for a multi-level voltage source inverter [J]. APEC'99: FOURTEENTH ANNUAL APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, CONFERENCE PROCEEDINGS, VOLS 1 & 2, 1999, : 509 - 514
- [36] Research on the Control Strategy of Capacitor Voltage Self-balance for Seven-level Inverter [J]. Gaodianya Jishu/High Voltage Engineering, 2022, 48 (07): : 2785 - 2793
- [37] Sinusoidal PWM For Flying Capacitor Voltage Balancing of a Six-Level Inverter [J]. 45TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY (IECON 2019), 2019, : 1979 - 1984
- [38] A novel hybrid multilevel inverter using DC-Link voltage combination [J]. 2003 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, 2003, : 159 - 162
- [40] Comparative Analysis of Hybrid NPP and NPC Seven-Level Inverter With Switched-Capacitor [J]. IEEE ACCESS, 2021, 9 : 85852 - 85863