Analysis of Leakage Current of HfO2/TaOx-Based 3-D Vertical Resistive Random Access Memory Array

被引:3
|
作者
Chen, Zhisheng [1 ,2 ]
Song, Renjun [1 ]
Huo, Qiang [2 ]
Ren, Qirui [2 ]
Zhang, Chenrui [1 ]
Li, Linan [1 ]
Zhang, Feng [2 ]
机构
[1] Beijing Jiaotong Univ, Sch Elect & Informat Engn, Beijing 100044, Peoples R China
[2] Chinese Acad Sci, Key Lab Microelect Device & Integrated Technol, Inst Microelect, Beijing 100029, Peoples R China
基金
中国国家自然科学基金;
关键词
resistive random access memory (RRAM); 3-D integration; self-selective cell (SSC); sneak path; leakage current; CROSSBAR ARRAY; RRAM; DEVICE; MODEL; CHALLENGES;
D O I
10.3390/mi12060614
中图分类号
O65 [分析化学];
学科分类号
070302 ; 081704 ;
摘要
Three-dimensional vertical resistive random access memory (VRRAM) is proposed as a promising candidate for increasing resistive memory storage density, but the performance evaluation mechanism of 3-D VRRAM arrays is still not mature enough. The previous approach to evaluating the performance of 3-D VRRAM was based on the write and read margin. However, the leakage current (LC) of the 3-D VRRAM array is a concern as well. Excess leakage currents not only reduce the read/write tolerance and liability of the memory cell but also increase the power consumption of the entire array. In this article, a 3-D circuit HSPICE simulation is used to analyze the impact of the array size and operation voltage on the leakage current in the 3-D VRRAM architecture. The simulation results show that rapidly increasing leakage currents significantly affect the size of 3-D layers. A high read voltage is profitable for enhancing the read margin. However, the leakage current also increases. Alleviating this conflict requires a trade-off when setting the input voltage. A method to improve the array read/write efficiency is proposed by analyzing the influence of the multi-bit operations on the overall leakage current. Finally, this paper explores different methods to reduce the leakage current in the 3-D VRRAM array. The leakage current model proposed in this paper provides an efficient performance prediction solution for the initial design of 3-D VRRAM arrays.
引用
收藏
页数:11
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