A 3.125Gbps timing and data recovery front-end with adaptive equalization

被引：4

作者：

Le, MQ ^{[1
]}

Van Engelen, J ^{[1
]}

Wang, H ^{[1
]}

Madisetti, A ^{[1
]}

Baumer, H ^{[1
]}

Buchwald, A ^{[1
]}

机构：

[1] Broadcom Corp, Irvine, CA 92618 USA

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

10.1109/VLSIC.2004.1346610

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 3.125Gbps timing and data recovery front-end is described. Adaptive discrete-time analog forward equalizers implemented in the receiver are used to cancel intersymbol interference. The coefficients in the analog equalizers are continuously adjusted by a digital adaptation loop. To save power, the digital adaptation loop operates at a 32x subsample rate. The timing recovery is 2x oversampled and uses these equalizers in its path for robust performance in the presence of intersymbol interference. A quad 3.125Gbps transceiver core has been fabricated in a standard 0.18mum CMOS process.

引用

页码：344 / 347

页数：4

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