A low-voltage low-power sigma-delta modulator with improved performance in overload condition

被引：1
|
作者：
Thompson, H [1 ]
Hufford, M [1 ]
Evans, W [1 ]
Naviasky, E [1 ]
机构：
[1] Cadence Design Serv, Columbia, MD 21045 USA
来源：
PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2004年
关键词：
D O I：
10.1109/CICC.2004.1358873
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 4(th)-order sigma-delta modulator is presented that offers significantly improved stability and SNR when the input is overloaded, compared to conventional single-bit modulators. The circuit combines the high linearity of a single-bit architecture with the increased stability of a multi-bit converter. Fabricated in a 0.13-mum CMOS logic process, it draws 208 muA from a 1.25V nominal supply. Clocked at 1.5 MHz, the input bandwidth is 150 Hz - 11 kHz, with SNR of 84 dB.
引用
收藏
页码：519 / 522
页数：4
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