Pseudorandom Bit Generator with Parallel Implementation

被引:1
|
作者
Stoyanov, Borislav [1 ]
Kordov, Krasimir [1 ]
机构
[1] Konstantin Preslavski Univ Shumen, Fac Math & Informat, Dept Comp Informat, Shumen, Bulgaria
关键词
Feedback with carry shift register; Editing generator; Parallel implementation; DESIGN; FCSR;
D O I
10.1007/978-3-662-43880-0_64
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
In this work we present a new filtering variant of pseudorandom bit generation which combines a 2-adic Feedback with Carry Shift Register and the Editing bit-search generator, based on I. Erguler and E. Anarim research. The generated algorithm uses dynamic blocks for data encryption. Shrinking the block is necessary if low memory is available. The algorithm divides the data block among the cores (the processors) and every core encrypts part of the data file. We show the advantage of using parallel implementation. The experimental statistical results establish the time difference of performance on serial and parallel encryption. The security of the generated bit streams are proven by using NIST, DIEHARD and ENT testing systems.
引用
收藏
页码:557 / 564
页数:8
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