Reconfigurable Distributed Fault Tolerant Routing Algorithm for On-Chip Networks

被引：0

作者：

Kumar, Manoj ^{[1
,2
]}

Pankaj ^{[1
]}

Laxmi, Vijay ^{[1
]}

Gaur, Manoj Singh ^{[1
]}

Ko, Seok-Bum ^{[2
]}

机构：

[1] Malaviya Natl Inst Technol, Dept Comp Engn, Jaipur, Rajasthan, India

[2] Univ Saskatchewan, Dept Elect & Comp Engn, Saskatoon, SK, Canada

来源：

PROCEEDINGS OF THE 2013 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS) | 2013年

关键词：

Networks on Chip; LBDR; fault-tolerance; dead-lock freedom;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Network on chip (NoC) is emerging as a promising solution to overcome bus bottleneck for future multi core chips. Fault tolerance and quality of service issues are potential challenges for NoCs. In this paper, we propose a cost-effective fault tolerant routing algorithm for irregular 2D mesh without use of routing tables. We use one hop visibility of Logic Based Distributed Routing (LBDR) to eliminate routing tables. This algorithm handles one or multiple single link faults within 2D mesh and uses reconfigured paths (minimal and/or non-minimal), if links fail. We use turn model based approach to avoid deadlocks. Since our method does not require virtual channels to achieve deadlock freedom, it remains area and power efficient.

引用

页码：290 / 295

页数：6

共 50 条

[1] A Fault-Tolerant Routing Algorithm Design for On-Chip Optical Networks
Xiang, Dong
Zhang, Yan
Shan, Shuchang
Xu, Yi
[J]. 2013 IEEE 32ND INTERNATIONAL SYMPOSIUM ON RELIABLE DISTRIBUTED SYSTEMS (SRDS 2013), 2013, : 1 - 9
[2] Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems
Nunez-Yanez, J. L.
Edwards, D.
Coppola, A. M.
[J]. IET COMPUTERS AND DIGITAL TECHNIQUES, 2008, 2 (03): : 184 - 198
[3] A New Fault Tolerant Routing Algorithm for Networks on Chip
Nehnouh, Chakib
Senouci, Mohamed
[J]. INTERNATIONAL JOURNAL OF EMBEDDED AND REAL-TIME COMMUNICATION SYSTEMS (IJERTCS), 2019, 10 (03): : 68 - 85
[4] Adaptive Stochastic Routing in Fault-tolerant On-chip Networks
Song, Wei
Edwards, Doug
Nunez-Yanez, Jose Luis
Dasgupta, Sohini
[J]. 2009 3RD ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, 2009, : 32 - +
[5] Reconfigurable fault tolerant routing for networks-on-chip with logical hierarchy
Schley, Gert
Ahmed, Ibrahim
Afzal, Muhammad
Radetzki, Martin
[J]. COMPUTERS & ELECTRICAL ENGINEERING, 2016, 51 : 195 - 206
[6] Fault-tolerant routing approach for reconfigurable networks-on-chip
Rantala, Pekka
Lehtonen, Teijo
Isoaho, Jouni
Plosila, Juha
[J]. 2006 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP PROCEEDINGS, 2006, : 107 - +
[7] A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs
Shi, Zewen
Zeng, Xiaoyang
Yu, Zhiyi
[J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2011, E94D (07): : 1386 - 1397
[8] A fault-aware dynamic routing algorithm for on-chip networks
Hosseini, Amir
Ragheb, Tamer
Massoud, Yehia
[J]. PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 2653 - 2656
[9] Fault Tolerant Distributed Routing Algorithms for Mesh Networks-on-Chip
Lehtonen, Teijo
Liljeberg, Pasi
Plosila, Juha
[J]. ISSCS 2009: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS,, 2009, : 149 - +
[10] A New Scalable Fault Tolerant Routing Algorithm for Networks-on-Chip
Kia, Hamed Sajjadi
Ababei, Cristinel
Srinivasan, Sudarshan
Jabeen, Shaista
[J]. 2015 IEEE 58TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2015,

← 1 2 3 4 5 →