Hardware Software Partitioning of Task Graph Using Genetic Algorithm

One of the addressable problem in the hardware software co-design is partitioning of functionality on CPU and ASIC/FPGA. The partitioning phase requires the decision for mapping and scheduling of application given as task graphs on a given CPU/ASIC combination. Hardware software partitioning is one of the critical steps to decide which components can be implemented in hardware and which ones implemented in software so that overall system is optimized. Based on a task graph model, this paper presents the optimum solution of problem using genetic algorithm techniques. Experimental results demonstrate that this method can achieve optimized partitioning in terms of cost and delay. A trade off between cost and delay has also been achieved to get the best possible solution.