Tunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric

An improved double-gate tunnel field-effect transistor structure with superior performance is proposed. The originality consists in the introduction of a low-k spacer that is combined with a high-k gate dielectric. Numerical simulations demonstrate that the use of the low-k spacer and high-k gate dielectric leads to a high on-current, I(ON), and reduced subthreshold slope. The proposed structure increases I(ON) by a factor of 3.8 and reduces the subthreshold slope by a factor of 2 compared to other structures described in literature.