Design of fast digit-serial adders using SFQ logic circuits

被引：3

作者：

Park, Heejoung ^{[1
]}

Yamanashi, Yuki ^{[1
]}

Yoshikawa, Nobuyuki ^{[1
]}

Tanaka, Masamitsu ^{[2
]}

Fujimaki, Akira ^{[3
]}

机构：

[1] Yokohama Natl Univ, Dept Elect & Comp Engn, Hodogaya Ku, Kanagawa 2408501, Japan

[2] Nagoya Univ, Dept Informat Engn, Chikusa Ku, Nagoya, Aichi 4648603, Japan

[3] Nagoya Univ, Dept Quantum Engn, Chikusa Ku, Nagoya, Aichi 4648603, Japan

来源：

IEICE ELECTRONICS EXPRESS | 2009年 / 6卷 / 19期

关键词：

SFQ circuit; superconducting device; josephson junction; digit-serial adder; adder; carry look-ahead adder;

D O I：

10.1587/elex.6.1408

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5 kA/cm(2) niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of +/- 15% at 25 GHz. Its maximum operation frequency was 30 GHz.

引用

页码：1408 / 1413

页数：6

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