A Low-Complexity Delta-Sigma Modulator (ΔΣ) for Low-Voltage, Low-Power Operation

被引:1
|
作者
Ocampo-Hidalgo, Juan J. [1 ]
Alducin-Castillo, Javier [1 ]
Garcia-Ortiz, Alberto [2 ]
Ezequiel Molinar-Solis, Jesus [3 ]
Gomez-Vieyra, Armando [1 ]
Vazquez-Alvarez, Ivan [1 ]
机构
[1] Univ Autonoma Metropolitana, Mexico City 02200, DF, Mexico
[2] Univ Bremen, D-28359 Bremen, Germany
[3] Inst Technol, Ciudad Guzman 49000, Mexico
关键词
Analog-digital conversion; low-power; low-voltage; sigma-delta modulation (Delta Sigma); switched-capacitor (SC) circuits;
D O I
10.1109/CJECE.2016.2542072
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In recent years, inverter-based sigma-delta (Delta Sigma) modulators have received great attention as a suitable approach for the design of low-voltage, low-power, switched-capacitor Delta Sigma. This method uses digital inverters as the active elements to construct the integrators in the Delta Sigma loop. In some applications, a reduced silicon area implementation is an important constraint; this demands the use of only one inverter in the integrator. This paper proposes to use the common-source amplifier as the building block to achieve the operation of integration instead of the digital inverter. This leads to the operation of the amplifier in strong inversion combined with low-voltage supply and compact chip area. The idea was confirmed with a prototype fabricated in a 0.5-mu m CMOS technology available through Metal Oxide Semiconductor Implementation Service (MOSIS). Using 250 kHz of sampling frequency, measurement results show a signal-to-noise and distortion ratio of 70 dB over a bandwidth of 125 Hz. The circuit consumes 38 mu W when powered from a single 1.5-V supply voltage and uses 200 x 260 mu m of active area. Circuit simulations in SPICE show the potential of this method to work with 450 mV of power supply in a 50-nm CMOS technology.
引用
收藏
页码:190 / 199
页数:10
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