Low Power Low Latency Floorplan-aware Path Synthesis in Application-Specific Network-on-Chip Design

In Application-Specific Networks-on-Chip (ASNoCs), both positions of the routers and the route for each communication trace of the application can be adjusted to suit the requirements. For an application, input to the current work is a gridded floorplan having fixed positions of cores and routers in it. Maximum physical link length between two routers has been taken as a constraint. For each edge in the application core graph, the proposed method selects a particular path amongst all possible paths, between two grid points. A set of paths is constructed, corresponding to each edge in the core graph, to minimize either the average packet latency or the total router power consumption of the network. The work also inserts junction routers at the intersection of two paths. Secondary routers or repeaters are inserted on a long link, to sustain a pre-specified maximum link length constraint. Alternative paths between routers requiring communication have been generated using a heuristic algorithm. From this, the path synthesis problem has been formulated using a set of linear equations. A Discrete Particle Swarm Optimization (DPSO) based solution has also been proposed for the problem. The path synthesis methodology has been tested with benchmark applications and compared with the shortest path based greedy approaches used by the other ASNoC synthesis methods. The results show a significant improvement in average packet latency and throughput. A power calculator has been developed that computes router power consumption as a function of traffic-load on the router and its number of input and output ports. With the help of the proposed power calculator, a power-aware path synthesis has been accomplished. Synthesized networks have been compared with the networks generated using the shortest path based methods. The proposed method consumes significantly less dynamic power compared to such greedy methods.