Modeling, Design and Verification Platform using SystemC AMS

被引：0

作者：

Li, Yao ^{[1
]}

Iskander, Ramy ^{[1
]}

Louerat, Marie-Minerve ^{[1
]}

机构：

[1] Univ Paris 06, Lab LIP6, F-75252 Paris, France

来源：

PROCEEDINGS OF THE FIFTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2014) | 2015年

关键词：

system-level design; circuit-level design; verification; system-level modeling; SystemC AMS;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper proposes a modeling, design and verification platform with a fast sizing and biasing methodology. We introduce a simple and efficient method to implement an interface between non-conservative system-level models and their circuit-level realizations. Simulation tools such as SystemC AMS and Spice simulators are combined with a sizing and biasing tool. Moreover, a transient simulation method is proposed to simulate non-linear dynamic behavior of complete mixed-signal systems. A verification testbench is introduced to monitor the effect of circuit-level non-idealities on system-level performances. The proposed platform is used to design and verify a 3-stage 6-bits Pipeline ADC. The simulation results prove the effectiveness of the proposed methodology.

引用

页码：39 / 46

页数：8

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