Modeling, Design and Verification Platform using SystemC AMS

This paper proposes a modeling, design and verification platform with a fast sizing and biasing methodology. We introduce a simple and efficient method to implement an interface between non-conservative system-level models and their circuit-level realizations. Simulation tools such as SystemC AMS and Spice simulators are combined with a sizing and biasing tool. Moreover, a transient simulation method is proposed to simulate non-linear dynamic behavior of complete mixed-signal systems. A verification testbench is introduced to monitor the effect of circuit-level non-idealities on system-level performances. The proposed platform is used to design and verify a 3-stage 6-bits Pipeline ADC. The simulation results prove the effectiveness of the proposed methodology.