共 50 条
- [41] BUILT-IN TEST OF CMOS STATE MACHINES WITH REALISTIC FAULTS - A SYSTEM PERSPECTIVE PROCEEDINGS OF THE IEEE 1989 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1989, : 667 - 670
- [42] Reduced March iC- Test for Detecting Ageing Induced Faults in Memory Address Decoders 2021 34TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2021 20TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID & ES 2021), 2021, : 193 - 198
- [43] Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2010, 26 (06): : 659 - 666
- [44] Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time Journal of Electronic Testing, 2010, 26 : 659 - 666
- [45] Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling 2011 IEEE 14TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS (DDECS), 2011, : 353 - 358
- [46] Slow write driver faults in 65nm SRAM technology: Analysis and march test solution 2007 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3, 2007, : 528 - +
- [48] Minimal march-based fault location algorithm with partial diagnosis for all static faults in random access memories PROCEEDINGS OF THE 2006 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2006, : 262 - +
- [50] An efficient March-based three-phase fault location and full diagnosis algorithm for realistic two-operation dynamic faults in Random Access Memories 26TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2008, : 95 - +