Bat Algorithm Based Low Power Mapping Methods for 3D Network-on-Chips

Mapping a task graph as a distribution of Intellectual Property (IP) cores onto a Network-on-Chip (NoC) is a NP-hard problem that significantly affects the performance metrics of the whole system including power, delay, load balance and heat. Intelligence optimization algorithms are widely used to solve mapping problems. Bat Algorithm (BA), a novel metaheuristic algorithm mimicking hunting behaviors of bats, which has never been applied in NoCs, is used in low power mapping methods for 3D NoCs in this paper for the first time. The BA based mapping algorithm shows better performance than other mainstream mapping algorithms in terms of the optimization efficiency and power consumption. However, the concept of the basic BA has obvious disadvantages. To improve the basic BA, we propose a Group-Searching Bat Algorithm (GSBA) that can better utilize individual bats. This improved mapping algorithm performs much better than the traditional BA, especially when the scale of the application graph is large.