An evaluation of the AAL and ATM protocols processing requirements for the network interfaces design

There are different possible design approaches to implement high-speed network interfaces. However, using the general purpose processing element in designing such interfaces can be very useful in providing very important features to these interfaces, such as simplicity, shorter developing cycle time, low cost, and flexibility to support protocol changes and perhaps new protocols. The main question that could be raised here is: can such an element provide the processing required by these high-speed interfaces efficiently? Also, where is the limit of such an element in supporting the processing of network interfaces? In other words, what is the scalability of network interfaces whose design is based on the general purpose-processing element? In this paper, we have measured the amount of processing required for the ATM network interfaces design supporting different transmission line speeds. Two methods have been used in our simulations. In the first, a simple RISC core simulator has been used to measure the processing required for an ATM network interfaces. In the second, a VHDL-based simulator has been developed to perform the same measurements. The results have shown that a general-purpose processing element, such as a simple and cost effective RISC core running at 81MHz, can be used as a processing element in a high-speed ATM network interfaces. Such core can support a wide range of transmission line speeds, up to 1.2 Gb/s and 2.4 Gb/s, for Reassembly and Segmentation functions respectively. Higher transmission line speeds can also be supported but with RISC core running at higher speeds.