Design of ATM AAL1 for circuit emulation

The ATM Adaptation Layer type 1 (AAL1) for constant bit rate service is developed for transporting conventional circuit-switched telecommunication service through ATM networks. In this paper, the AAL1 Segmentation and Reassembly (SAR) is designed and implemented by the Field Programmable Gate Array (FPGA). The SAR header is generated and processed in the FPGA, and the SAR payload is stored in a FIFO. A method for recovering the source clock, called Synchronous Residual Time Stamp (SRTS), is described and implemented. The designed AAL1 SAR FPGA is properly tested in a prototype board.