Escape Routing in Modern Area Array Packaging: An Analysis of Need, Trend, and Capability

被引:0
|
作者
Jaiswal, Bhanu [1 ]
Roy, Mihir K. [1 ]
Titus, Albert H. [2 ]
机构
[1] Intel Corp, Chandler, AZ 85226 USA
[2] SUNY Buffalo, Dept Elect Engn, Buffalo, NY 14260 USA
来源
关键词
Area array package; die-size; escape routing design; input/output (I/O) terminals; layer-count; micro-via; package substrate; trace width and spacing; two-layer routing; DENSITY; CHIP;
D O I
10.1109/TADVP.2009.2035304
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
With the increasing complexity in the die and package designs and ever increasing cost pressure in today's microelectronic industry, the design for input/output (I/O) routing has assumed a vital role in the overall product design. This scenario is primarily driven by the increase in the I/O terminal counts in both die and package. Several authors have already described the possibility of using various escape routing models in order to maximize the number of I/Os in a given area. However, these models suffer from many drawbacks and fail to address the importance of processing factors and the actual manufacturing conditions. Therefore, a new design guideline for escape routing has been developed to achieve the maximum I/O density under the actual manufacturing, processing and cost related constraints. The correlation between the real world constraints and their impact on I/O routing has been explored and used as a foundation for developing design guidelines. This approach has been presented through a comprehensive case study that covers various design scenarios, provides the right set of real world trade-offs that need to be considered and simultaneously highlights the drawbacks in existing models.
引用
收藏
页码:13 / 18
页数:6
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