Performance Analysis of QC-LDPC Codes with Girth 6 using Log Domain Sum Product Algorithm

被引：0

作者：

Mathur, Jitendra Pratap Singh ^{[1
]}

Pandey, Alpana ^{[1
]}

机构：

[1] Maulana Azad Natl Inst Technol, Elect & Commun Dept, Bhopal, India

来源：

PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON INVENTIVE COMPUTING AND INFORMATICS (ICICI 2017) | 2017年

关键词：

Regular QC-LDPC; Log Domain sum product Algorithm; 1/2 code rate; Bit error rate and girth 6;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper presents Bit error Rate performance Analysis of Quasi Cyclic Low Density Parity Check Codes (QC-LDPC) with girth 6 using Log Domain sum product and Simple Log Domain Sum Product Algorithm for Decoding. The approach to construct Parity Check matrix for LDPC codes is based on sparse Lower Upper decomposition. Then to create QC-LDPC matrix counter shifting, interleave mapping, Set XORing, Circulant Shifting and Randomization processes are being used. The constructed QC-LDPC codes is of a girth 6 on 1/2 code Rate have row weight 6 and column weight 3. Bit error rate performance is done through simulation to be calculated for various code length such as code I (960, 480), code II (1980, 990) and code III (1080, 540).

引用

页码：331 / 334

页数：4

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