Board level drop test reliability for MCP package

被引：0
|
作者：
Zhang Jing [1 ]
Du Maohua [1 ]
Feng Nufeng [1 ]
Taekoo, Lee [1 ]
机构：
[1] Samsung Semicond China R&D Co Ltd, Room B-404,Int Sci Pk, Suzhou 215021, Peoples R China
来源：
ICEPT: 2006 7TH INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING TECHNOLOGY, PROCEEDINGS | 2006年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
With the increasing requirement of thinner, higher density and multi-function product, MCP (Multi Chip Package) is becoming a more and more popular package. And for application in handheld systems, the package's resistance to drop impact becomes especially important. This study uses a simple DAQ system for the drop test according to JEDEC standard, discusses the effects of substrate pad denting, solder ball composition, and mold thickness on the reliability life, and through failure analysis the failure mechanism is explained.
引用
下载
收藏
页码：778 / +
页数：2
相关论文
共 50 条
  • [41] Board level drop test simulation for an advanced MLP
    Liu, Yumin
    Liu, Yong
    Irving, Scott
    ICEPT: 2007 8TH INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING TECHNOLOGY, PROCEEDINGS, 2007, : 680 - 684
  • [42] Board level reliability test of MPBGA assembly
    Chung, CS
    Zheng, PJ
    Lee, SC
    Wu, JD
    PROCEEDINGS OF THE 4TH INTERNATIONAL SYMPOSIUM ON ELECTRONIC MATERIALS AND PACKAGING, 2002, : 245 - 252
  • [43] Design for Board Trace Reliability of WLCSP under Drop Test
    Tee, Tong Yan
    Ng, Hun Shen
    Syed, Ahmer
    Anderson, Rex
    Khoo, Choong Peng
    Rogers, Boyd
    EUROSIME 2009: THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICRO-ELECTRONICS AND MICRO-SYSTEMS, 2009, : 217 - 224
  • [44] Package & Board Level Reliability Study of 0.35mm Fine Pitch Wafer Level Package
    Sun, Peng
    Liu, Jun
    Xu, Cheng
    Cao, Liqiang
    2017 18TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2017, : 322 - 326
  • [45] Optimization of thermomechanical reliability of board-level package-on-package stacking assembly
    Lai, Yi-Shao
    Wang, Tong Hong
    Wang, Ching-Chun
    IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2006, 29 (04): : 864 - 868
  • [46] A Finite Element Analysis of Board Level Drop Reliability Test and Analysis of Stress Buffer Effect of Polyimide
    Fujita, Mitsuru
    Anzai, Nobuhiro
    Sakamaki, Kazutoshi
    Kariya, Yoshiharu
    2013 IEEE 3RD CPMT SYMPOSIUM JAPAN (ICSJ 2013), 2013,
  • [47] Board level drop test analysis based on modal test and simulation
    Liu, Fang
    Meng, Guang
    Zhao, Mei
    Zhao, Junfeng
    JOURNAL OF ELECTRONIC PACKAGING, 2008, 130 (02) : 0210071 - 0210076
  • [48] Effects of different drop test conditions on board-level reliability of chip-scale packages
    Lai, Yi-Shao
    Yang, Po-Chuan
    Yeh, Chang-Lin
    MICROELECTRONICS RELIABILITY, 2008, 48 (02) : 274 - 281
  • [49] New/Old JEDEC Board Level Drop Reliability Test Standards Evaluation: Measurement and Simulation Study
    Chen, Ryan
    Wang, Ming-Han
    Lee, Sarah
    Ho, Janae
    Hu, Ian
    Shih, Sean
    2017 IEEE CPMT SYMPOSIUM JAPAN (ICSJ), 2017, : 211 - 215
  • [50] Impact of Board Configuration and Shock Loading Conditions for Board Level Drop Test
    Guruprasad, Pradosh
    Roggeman, Brian
    Pitarresi, James
    2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2011, : 2067 - 2072
12345