Thermal-fatigue life prediction equation for wafer-level chip scale package (WLCSP) lead-free solder joints on lead-free printed circuit board (PCB)

被引:8
|
作者
Lau, JH [1 ]
Shangguan, D [1 ]
Lau, DCY [1 ]
Kung, TTW [1 ]
Lee, SWR [1 ]
机构
[1] Agilent Technol, Santa Clara, CA 95052 USA
关键词
D O I
10.1109/ECTC.2004.1320324
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new thermal-fatigue life prediction equation for a class of lead-free solder alloys, 95.5wt%Sn3.9-4.0wt%Ag0.5-0.6wt%Cu is proposed in this investigation. The test vehicle consists of a lead-free solder-bumped WLCSP, lead-free PCB, and lead-free solder paste. The coefficients of the fatigue equation presented herein are determined by best fitted with the isothermal fatigue data of the test vehicle. Failure modes and locations of the failed samples are discussed.
引用
收藏
页码:1563 / 1569
页数:7
相关论文
共 50 条
  • [1] Wafer-level chip-scale package lead-free solder fatigue: A critical review
    Arriola, Emmanuel R.
    Ubando, Aristotle T.
    Gonzaga, Jeremias A.
    Lee, Chang-Chun
    [J]. ENGINEERING FAILURE ANALYSIS, 2023, 144
  • [2] Reliability Modeling of Lead-Free Solder Joints in Wafer-Level Chip Scale Packages
    Zhao, Jie-Hua
    Gupta, Vikas
    Lohia, Alok
    Edwards, Darvin
    [J]. JOURNAL OF ELECTRONIC PACKAGING, 2010, 132 (01) : 0110051 - 0110056
  • [3] A new thermal-fatigue life prediction model for wafer level chip scale package (WLCSP) solder joints
    Lau, JH
    Pan, SH
    Chang, C
    [J]. JOURNAL OF ELECTRONIC PACKAGING, 2002, 124 (03) : 212 - 220
  • [4] Reliability of wafer level chip scale package (WLCSP) with 96.5Sn-3.5Ag lead-free solder joints on build-up microvia printed circuit board
    Lau, JH
    Lee, SWR
    [J]. PROCEEDINGS OF INTERNATIONAL SYMPOSIUM ON ELECTRONIC MATERIALS AND PACKAGING, 2000, : 55 - 63
  • [5] Thermal-fatigue life prediction equation for plastic ball grid array (PBGA) SnAgCu lead-free solder joints
    Lau, John
    Lee, S. W. Ricky
    Song, Fubin
    Shangguan, Dongkai
    Lau, Dennis C.
    Dauksher, Walter
    [J]. ADVANCES IN ELECTRONIC PACKAGING 2005, PTS A-C, 2005, : 1013 - 1019
  • [6] Modeling and analysis of 96.SSn-3.SAg lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board
    Lau, JH
    Lee, SWR
    [J]. IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2002, 25 (01): : 51 - 58
  • [7] Creep analysis of wafer level chip scale package (WLCSP) with 96.5Sn-3.5Ag and 100In lead-free solder joints and microvia build-up printed circuit board
    Lau, JH
    Pan, SH
    Chang, C
    [J]. JOURNAL OF ELECTRONIC PACKAGING, 2002, 124 (02) : 69 - 76
  • [8] Effects of ramp-time on the thermal-fatigue life of SnAgCu lead-free solder joints
    Lau, J
    Dauksher, W
    [J]. 55TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2005 PROCEEDINGS, 2005, : 1292 - 1298
  • [9] Reliability of 96.5Sn-3.5Ag lead-free solder-bumped wafer level chip scale package (WLCSP) on build-up microvia printed circuit board
    Lau, JH
    Lee, SWR
    [J]. 2001 HD INTERNATIONAL CONFERENCE ON HIGH-DENSITY INTERCONNECT AND SYSTEMS PACKAGING, PROCEEDINGS, 2001, 4428 : 314 - 322
  • [10] The effects of temperature cyclic loading on lead-free solder joints of wafer level chip scale package by Taguchi method
    Jong, Wen-Ren
    Tsai, Hsin-Chun
    Chang, Hsiu-Tao
    Peng, Shu-Hui
    [J]. JOURNAL OF ELECTRONIC PACKAGING, 2008, 130 (01) : 0110011 - 01100110