Hardware coprocessor design for fingerprint image enhancement

Fingerprint biometric identification systems are widely used in applications where the security and the user's identity are considered as fundamental information. This paper shows a fingerprint image enhancement coprocessor which is specifically designed to be included in an embedded authentication system. The paper emphasizes the advantages offered by this structure against the classical solution based on high performance microprocessors. The designed architecture avoids the use of floating-point computations and speeds-up the resolution of the algorithm. Likewise, the coprocessor is segmented in several stages in order to reduce the critical path-delay, executing several intermediate operations in parallel leading to an increasing of the maximum clock frequency and throughput.