Gate-level exception handling design for noise reduction in high-speed VLSI circuits

This paper presents a novel design approach for addressing the pressing problem of noise and signal integrity in high-speed circuits. The approach uses a combination of gate-level redundancy in form of a shadow circuit, exception handling, and retry to tolerate random and delay faults that are of increasing concern in modern circuits. An empirical evidence of the delay/random fault problem is developed and a scheme to press clocking frequency beyond traditional limit is presented. The results show that approximately 10% improvement in clocking frequency can be achieved with almost negligible performance penalty and 5%-20% area overhead for the benchmark circuits studied.