Design and Implementation of High-Speed Energy-Efficient Carry Select Adder for Image Processing Applications

The design of High-Speed and Energy-Efficient Carry Select Adder (CSLA) for image processing applications results in the reduction of the number of transistors leading to less delay and high power dissipation. The adders are the basic building blocks of each processing unit. The novelty of this paper includes the proposal of a new CSLA which includes Final Selection Unit (FSU), Primary Carry Unit (PCU), Wave Carry Unit (WCU1, WCU2), these are split up into the suitable width in terms of bit. These blocks are integrated with functional blocks using random logic for which the output and input include only the carry function. The carry estimation is skipped in the first stage of every block of bit-slice. The design is synthesized using 180 nm CMOS technology for different input bit widths. The proposed CSLA shows a significant reduction in delay and area compared to existing adders.