Impact of Self-Heating in Wire Interconnection on Timing

被引:0
|
作者
Kanamoto, Toshiki [1 ]
Okumura, Takaaki [2 ]
Furukawa, Katsuhiro [3 ]
Takafuji, Hiroshi [4 ]
Kurokawa, Atsushi [5 ]
Hachiya, Koutaro [3 ]
Sakata, Tsuyoshi [6 ]
Tanaka, Masakazu [7 ]
Nakashima, Hidenari [8 ]
Masuda, Hiroo [1 ]
Sato, Takashi [9 ]
Hashimoto, Masanori [10 ]
机构
[1] Renesas Technol Corp, Kodaira, Tokyo 1878588, Japan
[2] Semicond Technol Acad Res Ctr, Kanagawa 2220033, Japan
[3] Jedat Inc, Tokyo 1030013, Japan
[4] RICOH Co Ltd, Ikeda, Osaka 5638501, Japan
[5] Sanyo Elect Co Ltd, Gifu 5030195, Japan
[6] Fujitsu Microelect Ltd, Akiruno 1970833, Japan
[7] Panasonic Corp, Nagaokayo 6178520, Japan
[8] NEC Elect Corp, Yokohama, Kanagawa 2218668, Japan
[9] Kyoto Univ, Kyoto 6068501, Japan
[10] Osaka Univ, Suita, Osaka 5650871, Japan
来源
IEICE TRANSACTIONS ON ELECTRONICS | 2010年 / E93C卷 / 03期
关键词
interconnect; delay variation; parasitic resistance; thermal; temperature; self-heat; SoC;
D O I
10.1587/transele.E93.C.388
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper evaluates impact of self-heating in wire interconnection on signal propagation delay in an upcoming 32 nm process technology. using practical physical parameters This paper examines a 64-bit data transmission model as one of the most heating cases Experimental results show that the maximum wire temperature increase due to the self-heating appears in the case where the ratio of interconnect delay becomes largest compared to the driver delay However, even in the most significant case which induces the maximum temperature rise of 11 0 degrees C. the corresponding increase in the wire resistance is 1 99% and the resulting delay increase is only 1 15%. as for the assumed 32 nm process A part of the impact reduction of wire self-heating on timing comes from the size-effect of nano-scale wires
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页码:388 / 392
页数:5
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