A low complexity UWB circuit transceiver architecture for low cost sensor tag systems

被引:7
|
作者
Stoica, L [1 ]
Tiuraniemi, S [1 ]
Repo, H [1 ]
Rabbachin, A [1 ]
Oppermann, I [1 ]
机构
[1] Univ Oulu, Ctr Wireless Commun, SF-90100 Oulu, Finland
关键词
UWB transceiver; UWB pulse generator; DLL based clock synthesis;
D O I
10.1109/PIMRC.2004.1370863
中图分类号
TN [电子技术、通信技术];
学科分类号
0809 ;
摘要
This paper presents the architecture of a low power, low complexity Ultra Wideband (UWB) transceiver circuit. The circuit is designed for low data rate, low cost applications with built in location and tracking capabilities. The system is based on a non-coherent architecture which enables the receiver to be extremely simple and largely insensitive to the transmitted pulse shape. The circuit presented contains the oscillator, the transmitter, the receiver and baseband digital signal processing (DSP) block. The oscillator contains the quartz oscillator, a delay locked-loop (DLL) and edge combiner for clock multiplication to generate a 528 MHz timing signal for pulse generation. The transmitter contains a second DLL to fix the delay of the UWB pulse, the UWB pulse generator and antenna. The transmitted UWB pulse is presented. The receiver contains low noise amplifier, variable gain amplifier, squaring circuits, integrators for energy collection, 4 bit analogue-to-digital converters (ADC), digital control logic, integrator and gain selection logic block and detection/bit decision block. The circuits are designed in a 0.35 mum Si-Ge BiCMOS process from Austria Microsystems.
引用
收藏
页码:196 / 200
页数:5
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